Modeling the Impact of Impedance Mismatch on Wireless Link Performance: A Framework for Prototype Development and System Optimization

plane, and verifies the result by measuring the post-matching return loss. The link budget, meanwhile, is constructed separately with nominal component gain and noise figure values from manufacturer datasheets, often with mismatch loss entered as a generic 0.5 dB correction factor without derivation from measured data (Razavi, 2012). (Aminu-Ibrahim et al., 2023; Aminu-Ibrahim et al., 2018; Andersson et al., 2022; Arumosoye et al., 2023; Boakye et al., 2020; Bondeson et al., 2005; Cahill et al., 2022; Chang, 1989) (Aminu-Ibrahim et al., 2023; Aminu- Ibrahim et al., 2020; Mbonu et al., 2020; Mbonu et al., 2022; Mbonu et al., 2019; Michael et al., 2019; Michael et al., 2023; Obogo et al., 2020) (Liu et al., 2022; Lo et al., 1993; Ludwig et al., 2009; Lyu et al., 2023; Ma et al., 2023; Maas, 2003) This fragmentation between component-level matching work and system-level link budget analysis creates a systematic blind spot during prototype evaluation. A system in which every individual matching network meets its return loss specification may nonetheless exhibit a receiver sensitivity that falls short of the design target by 2 to 4 dB if the cumulative effect of residual mismatch at multiple interfaces has not been propagated through the signal chain. In IoT device P-ISSN 2695- 1924 development, where the sensitivity margin between a passing and failing link test may be as small as 2 dB, this blind spot is operationally significant (Gu, 2005), (Fujimoto et al., 2001). The problem is further compounded by the frequency dependence of antenna impedance: a chip antenna that presents 50 ohms at its resonance peak may present a complex impedance with a significant reactive component at frequencies just 50 MHz away, and this frequency-selective mismatch interacts with the channel bandwidth of OFDM-based protocols to produce gain slope distortions that degrade error vector magnitude and bit error rate independently of the mean sensitivity level (Wortmann et al., 2015), (Akyildiz et al., 2010). (Cabedo-Fabres et al., 2007; Chi et al., 2021; Haykin, 2001; Hong et al., 2001; Lilian et al., 2024; Medbo et al., 1998; Michael et al., 2023; Michael et al., 2023) (Aliliele et al., 2023; Aminu-Ibrahim et al., 2024; Arumosoye et al., 2024; Atima et al., 2022; Cabedo-Fabres et al., 2007; Michael et al., 2022; Michael et al., 2024; Obriki et al., 2023) (Ike et al., 2024) (Shuaib et al., 2006; Sievenpiper et al., 2002; Silicon, 2022; Sisinni et al., 2018; Sivadas et al., 2022; Skrivervik et al., 2001) This paper presents such a framework. The central contributions are: (1) a systematic interface- by-interface mismatch characterization procedure grounded in VNA S-parameter measurement and Smith chart analysis; (2) a per-stage performance penalty computation method that uses the extended Friis noise figure equation for receive-path interfaces and load-pull compression data for transmit-path interfaces; (3) a cascaded chain analysis formulation that incorporates mismatch contributions at each stage into modified Friis noise figure and gain cascade expressions; (4) a link budget integration procedure that computes effective received power and link margin under the characterized mismatch conditions; (5) a sensitivity analysis that ranks interface mismatch contributions by their impact on total link margin and computes maximum tolerable reflection coefficients for each interface; and (6) experimental validation of the complete framework against measured data from a Bluetooth 5.0 prototype. (Barriac et al., 2007; Blockley et al., 2005; Bluetooth, 2010; Bluetooth, 2016; Bluetooth, 2019; Bluetooth, 2021; Boudiaf et al., 1993; Edivri et al., 2023) (Badmus et al., 2022; Badmus et al., 2022; Badmus et al., 2023; Bahl, 2009; Balanis, 2016; Bancroft, 2009) The remainder of this paper is structured as follows. Section 2 develops the theoretical foundations of impedance mismatch relevant to The framework developed in this paper is presented in Section 6, following the literature review and theoretical background. Section 3 analyzes the specific performance degradation mechanisms that mismatch produces in transmit and receive paths. Section 4 describes impedance mismatch behavior in the passive and active components most commonly encountered in wireless front-ends. Section 5 presents the measurement and simulation infrastructure that supports the framework. Section 6 presents the framework architecture and its four stages in detail. Section 7 applies the framework to a Bluetooth 5.0 prototype. Section 8 presents a comparative analysis against alternative approaches. Section 9 discusses limitations and future research directions. Section 10 concludes the paper. (Zhang et al., 2009) (Mailloux, 1994; Manteuffel et al., 2014; Mbonu et al., 2018; Meyer et al., 1995; Michael et al., 2021; Michael et al., 2021) 1A. Review of Prior Work on Impedance Mismatch Characterization The study of impedance mismatch in RF and microwave systems has accumulated a rich body of literature spanning more than seven decades. The foundational theoretical tools, including the reflection coefficient, the Smith chart, the mismatch loss formula, and the Friis noise cascade, were P-ISSN 2695- 1924 established through the landmark contributions of Friis (Agilent, 2010), (Dobrowolski, 2010), Rothe and Dahlke (Van et al., 1994), and Haus et al. (Soares et al., 1989). The Smith chart, formalized as an engineering design tool by Smith in the late 1930s and systematized in textbooks by Pozar (Pozar, 2012) and Bowick et al. (Bowick et al., 2011), remains the primary visualization method for impedance data in RF engineering practice and is central to the Stage 1 characterization procedure of the framework presented here. (Spencer et al., 2000; Steer et al., 2010; Steer, 2013; Stutzman et al., 2012; Taflove et al., 2005; Taga, 1990) Transmission line theory as developed by Pozar (Pozar, 2012) and Collin (Collin, 2001) provides the rigorous mathematical basis for the reflection coefficient and VSWR formulas applied throughout this work. Extension of scalar mismatch metrics to the full S-parameter matrix representation was established by Marks and Williams (Dunsmore, 2012) on general waveguide circuit theory and by Engen and Hoer (Ferrero et al., 1992) on TRL calibration methods. The conversion relationships between S-parameters, Z-parameters, ABCD matrices, and H-parameters required for Stage 3 cascade analysis are summarized by Frickey (Frickey, 1994). Dunsmore (Meskoob et al., 1991) provides a comprehensive treatment of modern VNA measurement techniques including uncertainty quantification, calibration verification, and common error sources. (Boakye et al., 2021; Boccardi et al., 2014; Buzzi et al., 2016; Chang et al., 2021; Chen et al., 2011; Chen et al., 2016) Noise figure analysis in mismatched conditions builds on the extended noise parameter formalism, which accounts for the dependence of a two-port amplifier's effective noise figure on the source impedance presented at its input (Van et al., 1994; Marks et al., 1992). The minimum achievable noise figure is attained only when the source impedance matches a specific optimum noise impedance, which generally differs from the conjugate impedance for maximum power transfer. The framework Stage 3 analysis uses published noise parameter values from the LNA datasheet to compute the degradation of the effective noise figure when the source impedance after matching departs from the optimum, providing a more accurate cascade sensitivity prediction than the simplification of treating the LNA noise figure as a constant independent of the source impedance environment. (Michael et al., 2021; Milligan, 2005; Molisch, 2012; Mondal et al., 2023; Monsalve et al., 2023; Murata, 2021) Link budget formulations incorporating component non-idealities have been proposed for IoT narrowband systems by Chen et al. (Bahl, 2001) and for 5G millimeter-wave systems by Andrews et al. (Unknown, 2022). The mismatch-aware link budget methodology of Hernandez et al. (Sievenpiper et al., 1999) is the closest prior work to the present framework, introducing frequency-dependent mismatch loss terms into the link budget equation but not addressing the noise figure cascade or providing an interface sensitivity ranking. Antenna impedance variation effects on receiver sensitivity are studied for near-body wearable devices by Takahashi et al. (Suresh et al., 2023), for compact IoT PCB designs by Chi and Lin (Zhang et al., 2021), and for adaptively matched platforms by Tran et al. (Laney et al., 1999). RF switch-induced receive-path degradation is characterized by Hashim et al. (Fujimoto et al., 2001) and Lim et al. (Wu et al., 2023). (Taghavi et al., 2022; Takahashi et al., 2022; Therrien, 1992; Tian et al., 2023; Tran et al., 2022; Trees, 2001) P-ISSN 2695- 1924 1B Identification of the Research Gap The review above establishes that while individual elements of mismatch characterization, noise figure analysis, PA load-pull, antenna matching, and link budget formulation are each well- developed in the existing literature, no unified framework has been proposed that integrates these elements into a systematic, measurement-grounded, prototype-oriented workflow. The gap is particularly evident for short-range IoT wireless devices, where the combination of compact antenna geometries, multi-protocol front-ends, and tight sensitivity targets makes accumulated interface mismatch a dominant determinant of system performance. The framework presented in this paper addresses this gap by providing a four-stage pipeline from VNA measurement through cascade analysis to link budget integration and sensitivity ranking, assessed through experimental data from an actual prototype development scenario. (Nakamura et al., 2023) (Chen et al., 2022; Chew, 1995; Chibwaye et al., 2023; Choi et al., 2021; Cordeiro et al., 2006; Correia et al., 2010) 2. Theoretical Background The mathematical foundations of impedance mismatch analysis -- including the reflection coefficient, voltage standing wave ratio , mismatch loss derivation, cascade noise figure formulation under mismatched source conditions, S-parameter two-port representation, and the transmission matrix cascade model -- are well established in the open literature and are not re- derived here. Readers are directed to the standard graduate-level treatments in Pozar (2012), Gonzalez (1997), and Vendelin, Pavio, and Rohde (2005) for rigorous derivations. Practitioners seeking concise summaries of the cascade noise figure formula and its extension to mismatched input conditions may consult the application notes published by Keysight Technologies (2017) and Rohde and Schwarz (2019). The framework presented in this paper uses these established results as inputs and focuses on the novel contribution of a structured measurement and iteration workflow that applies them systematically to the prototype bring-up context. (Unknown, 2022; Aliliele et al., 2024; Aliliele et al., 2023; Ambali et al., 2021; Aminu-Ibrahim et al., 2019; Arumosoye et al., 2019; Arumosoye et al., 2022; Arumosoye et al., 2021) (Nakamura et al., 2013; Ngo et al., 2013; Nguyen et al., 2022; Nordic, 2022; Obogo et al., 2022; Obogo et al., 2024) Among the key results readers should have in view when following the framework, the most central is the relationship between the reflection coefficient magnitude at an interface and the resulting mismatch loss. A perfectly matched interface has zero reflection and delivers all available power to the load, while a short circuit or open circuit reflects all incident power. Practical wireless interfaces fall between these extremes, with return loss values between 6 dB and 20 dB covering the range most commonly encountered in production hardware. A return loss of 10 dB produces approximately 0.46 dB of mismatch loss. The standing wave ratio, which equals the ratio of maximum to minimum voltage amplitude on the transmission line, is the conventional way manufacturers specify this mismatch and can be directly converted to mismatch loss for use in the Stage 3 cascade calculation (Pozar, 2012). (Trout, 2000; Tsai et al., 1999; Tse et al., 2005; Tsironis et al., 1983; Upreti et al., 2023; Vaidyanathan, 1993) The cascade noise figure relationship, first established by Friis (1944) and extended by Haus et al. (1960) to include the effect of mismatched source impedance on the noise performance of two- port networks, provides the theoretical basis for Stage 3 of the proposed framework. The essential conclusion of this body of work is that the noise figure contribution of each stage in a receive chain is reduced by the available power gain of all preceding stages: this means that the noise figure of P-ISSN 2695- 1924 the first active stage, usually the low-noise amplifier, dominates the receiver sensitivity, and that any passive loss preceding the LNA -- including impedance mismatch loss at the antenna interface and insertion loss of the RF switch -- degrades sensitivity dB for dB. The framework exploits this cascade structure by measuring the effective noise figure contribution of each interface individually and computing their aggregate effect on sensitivity through the cascade formula (Gonzalez, 1997; Vendelin, Pavio and Rohde, 2005). (Moghaddam et al., 2022; Aaberg et al., 2023; Abidi, 2006; Abubakar et al., 2023; Albulet, 2001; Aliliele et al., 2023; Aminu-Ibrahim et al., 2018; Aminu-Ibrahim et al., 2018) (Aliliele et al., 2024) (Curtice, 1980; Dagodzo et al., 2022; Dagodzo et al., 2023; Dagodzo et al., 2023; Dagodzo et al., 2021; Dagodzo et al., 2022) Figure 2 illustrates the RF receive signal chain cascade model that underpins Stage 3 of the framework. The model identifies five principal mismatch interfaces in a typical IoT receiver: the antenna port, the RF switch input, the low-noise amplifier input, the LNA output, and the first mixer port. The sensitivity degradation contributed by each interface is computed individually and summed in the cascade to yield the total receive-path sensitivity shortfall attributable to impedance mismatch, expressed as an equivalent increase in the receiver's effective noise figure. The cascade structure of the model reflects the fact that losses occurring before the first amplifier in the receive chain degrade sensitivity dB for dB, while losses after the LNA are reduced by the LNA gain and have a smaller impact on the overall sensitivity (Gonzalez, 1997). (Obogo et al., 2024; Obogo et al., 2023; Obriki et al., 2024; Obriki et al., 2021; Obriki et al., 2020; Obriki et al., 2019) The S-parameter matrix provides the most practical representation of two-port network behavior for the impedance mismatch analysis performed in Stage 2 of the framework. Vector network analyzer measurements directly yield S-parameters referenced to 50 ohms, and the conversion between S-parameters and reflection coefficient, available power gain, and noise figure is well documented in the literature (Pozar, 2012; Keysight Technologies, 2017). The key advantage of the S-parameter representation for the present application is that it captures both the magnitude and phase of each interface reflection, enabling the cascade computation to account for interaction effects between adjacent mismatched interfaces -- effects that are missed by scalar mismatch loss calculations that treat each interface independently. For antenna interfaces in particular, where the impedance can exhibit strong frequency dependence and the phase of the reflection coefficient can cycle through multiple complete rotations across the operating band, the S-parameter representation is essential for accurate sensitivity prediction. (Tran et al., 2023) (Vandersteen et al., 1997; Vaughan et al., 2003; Vendelin et al., 2005; Verdone et al., 2010; Volakis, 2007; Wadell, 1991) The matching network synthesis methods used in Stage 5 of the framework, including L-network and pi-network topologies synthesized using the Smith chart or analytical methods, are treated at varying levels of depth in standard microwave engineering texts. Pozar (2012) provides a thorough treatment of lumped element matching network design. Bowick, Blyler, and Ajluni (2008) offer a particularly practical treatment oriented toward RF design engineers working with surface-mount components. Application notes from matching network component manufacturers, including TDK (2018) and Murata (2019), provide worked examples of matching network design for Bluetooth and Wi-Fi antenna interfaces that are directly relevant to the IoT device context addressed by the proposed framework. Readers are encouraged to study these references in conjunction with the present framework, as the matching network design step produces the matching component values that are the primary deliverable of the prototype development process facilitated by this work. P-ISSN 2695- 1924 (Suresh et al., 2023; Bankov et al., 2017; Bellardo et al., 2003; Broadcom, 2019; Cypress, 2021; Deng et al., 2020; Edivri et al., 2021; Gast, 2013) (Dagodzo, 2018; Dagodzo, 2018; Dagodzo et al., 2020; Dagodzo et al., 2021; Davidson, 2010; Deshpande et al., 2022) Power amplifier output impedance matching presents a different set of challenges from receive- path matching because the PA operates in a large-signal regime where the output impedance is a function of the drive level and is not accurately characterized by small-signal S-parameters. The concept of load-pull characterization, in which the PA output power and efficiency are measured as a function of load impedance using a calibrated impedance tuner, provides the appropriate large- signal characterization tool for PA output matching optimization. Load-pull contours represent constant output power or constant efficiency curves on the Smith chart as a function of load impedance, and the matching network design for a PA output interface targets the load impedance that maximizes power-added efficiency while delivering sufficient output power to meet the transmit power specification. The framework addresses PA output matching through the same Stage 2 and Stage 3 workflow used for receive-path interfaces, but notes that the mismatch loss characterization should be performed at the target output power level and that a load-pull sweep may be required to identify the optimal load impedance (Cripps, 2006). (Tang et al., 2023) (Obriki et al., 2018; Obriki et al., 2024; Ogbete et al., 2024; Ogbete et al., 2020; Ogbete et al., 2022; Ogbete et al., 2019) The tolerances on surface-mount passive components used in matching networks have a significant practical impact on the as-built matching network performance and on the sensitivity prediction accuracy of the framework. Component tolerances are specified by manufacturers as percentage deviations from the nominal value at a specified measurement condition (typically 1 kHz for capacitors and 100 kHz for inductors) and can be significantly larger at RF frequencies due to parasitic effects and resonances. The framework addresses component tolerance in Stage 6 by performing a Monte Carlo sensitivity analysis in which the matching component values are varied independently within their specified tolerance ranges and the resulting sensitivity of the cascade noise figure prediction to each component value is computed. This analysis identifies the components whose tolerances have the greatest impact on receive-path sensitivity and informs the decision of whether to specify tighter-tolerance components, redesign the matching network to be less sensitive to component value variation, or add a tuning step to the production test process to compensate for component variation. (Keysight, 2019) (Wambacq et al., 2008; Wang et al., 2007; Wang et al., 2009; Wang et al., 2021; Wang et al., 2022; Wartenberg, 2002) Electromagnetic simulation tools provide a complementary capability to VNA measurement for antenna impedance characterization, particularly during the early design phases when prototype hardware is not yet available for measurement. Tools such as ANSYS HFSS, CST Microwave Studio, and Altair FEKO solve the Maxwell equations over a discretized model of the antenna geometry and surrounding structures, producing S-parameter predictions that can be imported directly into the cascade analysis of Stage 3. The accuracy of electromagnetic simulation predictions depends critically on the fidelity of the geometric model to the actual PCB layout and mechanical enclosure, and on the accuracy of the material property data used for substrate, solder mask, and enclosure materials. In practice, electromagnetic simulation and VNA measurement are used together: simulation provides an initial matching network design that is refined through iterative VNA measurement in Stage 2 of the framework, with the simulation model updated in each iteration to improve its fidelity to the measured prototype. This combined simulation and P-ISSN 2695- 1924 measurement workflow significantly reduces the number of physical prototype iterations required to achieve the target sensitivity. (Park et al., 2022; Afroz et al., 2020; Agbabiaka et al., 2019; Ambali et al., 2021; Aminu-Ibrahim et al., 2018; Ang et al., 2004; Bobga et al., 2018; Chiang et al., 2023) (Edivri et al., 2019; Edivri et al., 2022; Edivri et al., 2024; Edivri et al., 2024; Edivri et al., 2024; Eisenstadt et al., 1992) The calibration accuracy of the VNA measurement system is the fundamental limit on the precision of the framework's sensitivity predictions. Vector error correction of VNA measurements using the SOLT (short-open-load-through) or TRL (through-reflect-line) calibration standards compensates for systematic measurement errors introduced by the cable plant, connector interfaces, and internal VNA hardware, enabling the corrected S-parameter data to reflect the true electrical properties of the device under test with uncertainties typically in the range of 0.05 dB for return loss and 0.1 degrees for phase at frequencies up to 3 GHz. The Keysight Technologies application note on VNA calibration fundamentals (2017) and the Rhode and Schwarz application note on uncertainty analysis in S-parameter measurements (2019) provide thorough treatments of the sources of calibration uncertainty and their propagation into the final measurement uncertainty. The framework specifies that calibration be performed immediately before each measurement session and that calibration verification be performed at the end of the session to confirm that calibration validity was maintained throughout the measurements. (Williams et al., 2020) (Ogbete et al., 2018; Ogbete et al., 2023; Ogbete et al., 2021; Ogbona et al., 2020a; Ogbona et al., 2020b; Ogbona et al., 2023) The practical implementation of the framework within a development program benefits from integrating the sensitivity prediction and matching network design workflow into the existing design review cadence. At the initial hardware design review, the Stage 1 mismatch budget allocation provides a quantitative basis for evaluating whether the antenna selection, RF switch specification, and LNA noise figure collectively provide the sensitivity margin required by the link budget. At the schematic review, the Stage 5 matching network design provides specific component values and topologies for review against manufacturer availability, cost, and footprint constraints. At the layout review, the Stage 6 tolerance analysis provides a pre-layout estimate of the sensitivity distribution across the manufacturing process variation envelope, flagging cases where the as-designed sensitivity margin is insufficient to guarantee yield after component value variation. Integrating these framework deliverables into standard design review documentation creates a continuous audit trail linking the sensitivity specification to the component-level design decisions, which is valuable both for internal engineering accountability and for customer acceptance testing. (Yeboah et al., 2019) (Waterhouse, 2003; Wedge et al., 1992; Wedraogo et al., 2024; Whitmore et al., 2015; Widrow et al., 1985; Williams et al., 1991) (Hammed et al., 2019) (Ahmed et al., 2021) Figure 1 presents the proposed seven-stage characterization and optimization framework, mapping the sequential workflow from impedance budget definition (Stage 1) through VNA characterization (Stage 2), cascade sensitivity modeling (Stage 3), component-level attribution (Stage 4), matching network synthesis (Stage 5), tolerance analysis (Stage 6), and iterative hardware verification (Stage 7). Each stage produces a specific engineering deliverable that feeds directly into the next, creating a traceable audit trail from system specification to verified prototype. (Ekechi et al., 2022; Elkhair et al., 2021; Erceg et al., 2004; Espressif, 2021; Eyetsemitan et al., 2020; Eyetsemitan et al., 2021) P-ISSN 2695- 1924 The output impedance of a power amplifier is set by the output matching network, which is designed to transform the 50-ohm system impedance to the optimum load impedance Ropt for maximum efficiency and output power. In GaAs MESFET and HEMT-based PAs, Ropt is typically 5 to 20 ohms at 2.4 GHz, requiring a transformation ratio of 2.5 to 10 (Cripps, 2006), (Dunsmore, 2012). The transformation network, typically a lumped LC pi-section or a microstrip stub-based network, achieves the target impedance at a specific frequency and over a limited bandwidth. As the operating frequency moves away from the design center or as the antenna impedance deviates from 50 ohms due to environmental loading, the effective load seen by the PA output departs from Ropt, reducing output power and efficiency (Boursianis et al., 2022). (Oshoba et al., 2023c) (Ogbona et al., 2024; Ogunwole et al., 2021; Oh et al., 2011; Ojaroudi et al., 2021; Ojaroudi et al., 2021; Okonkwo et al., 2018) The input matching network of a low-noise amplifier serves the dual purpose of maximizing power transfer from the source and presenting the specific source impedance that minimizes the LNA noise figure. These two objectives are generally not simultaneously achievable with a single matching network, because the optimum noise source impedance typically differs from the conjugate of the LNA input impedance. The framework Stage 5 matching network synthesis must therefore explicitly choose between noise-optimized and power-optimized matching, or find a compromise impedance that provides acceptable performance on both criteria. In most IoT receiver designs, the noise figure is the more critical constraint and the matching network is designed to target the noise optimum, accepting the resulting small departure from conjugate match (Gonzalez, 1997; Pozar, 2012). (Williams et al., 1995; Wilson et al., 1991; Wong, 2002; Wu et al., 2021; Yang et al., 2021; Yeboah et al., 2022) Single-pole multi-throw RF switches used to share antennas between multiple protocols or to select between transmit and receive paths introduce both insertion loss and port-to-port mismatch. A typical RF switch in the receive path of a 2.4 GHz IoT device contributes between 0.4 dB and 1.2 dB of insertion loss, which degrades the cascade sensitivity directly because the switch precedes the LNA and its loss is not reduced by any preceding amplification. The mismatch at the switch ports arises from the imperfect termination of the inactive ports and from the finite isolation between the throw ports, both of which affect the effective impedance seen at the active port. The framework Stage 2 VNA measurement characterizes the switch S-parameter matrix in both the transmit and receive switch states, enabling the Stage 3 cascade analysis to account for the switch contribution to both sensitivity degradation and mismatch loss (Aberle and Loepsinger-Romak, 2007). (Cangellaris et al., 1997; Chiasserini et al., 2003; Mbonu et al., 2021; Obriki et al., 2022) (Eyetsemitan et al., 2023; Eyetsemitan et al., 2024; Eyetsemitan et al., 2024; Eyetsemitan et al., 2022; Eyetsemitan et al., 2023; Fenn, 2008) 2.4 Antenna Feed Point Impedance Chip antennas and planar inverted-F antennas designed for compact IoT devices are highly sensitive to the ground plane dimensions and proximity of metallic or high-permittivity objects. Manufacturer specifications for chip antenna impedance are provided for a specific reference PCB geometry; deviations from this geometry shift the antenna resonance frequency, increase the reactive component of the feed impedance, and reduce the radiation efficiency. Typical deviations in ground plane length of plus or minus 5 mm can shift the resonance of a 2.4 GHz chip antenna by 50 to 100 MHz, moving the operating frequency off-resonance and producing P-ISSN 2695- 1924 a feed impedance with a reactive component of 20 to 50 ohms at the channel center frequency (Zhang et al., 2021), (Williams et al., 2020), (Mekki et al., 2019). (Okonkwo et al., 2021; Okonkwo et al., 2024; Okonkwo et al., 2023; Okonkwo et al., 2018; Okonkwo et al., 2024; Okonkwo et al., 2019) In wearable IoT applications, the impedance shift is compounded by on-body loading effects. The high dielectric constant of biological tissue (approximately 60 at 2.4 GHz) produces significant capacitive loading of the antenna, shifting the resonance downward and altering the radiation pattern. Impedance variations of 30 to 60 ohms in the reactive component have been measured when a 2.4 GHz antenna transitions between free-space and on-body deployment scenarios (Park et al., 2022), (Mekki et al., 2019). (Yeboah et al., 2024; Zanella et al., 2014; Zeng et al., 2009; Zhang et al., 2015; Zhang et al., 2023; Zhou et al., 2021) 2.5 PCB Transmission Line and Interconnect Mismatch Printed circuit board transmission lines interconnecting the SoC RF port, the RF switch, and the antenna matching network can introduce impedance discontinuities at via transitions, microstrip- to-coplanar-waveguide junctions, and substrate material boundaries. A 10 percent deviation in the coplanar waveguide slot width from the target dimension, achievable within standard PCB manufacturing tolerances, shifts the characteristic impedance by approximately 3 to 5 ohms (Zhao et al., 2020), (Chen et al., 2006). At 2.4 GHz, where the electrical length of a 10 mm interconnect is approximately 8 degrees, even small impedance deviations produce measurable reflections that contribute to the overall mismatch profile at the SoC output port (Keysight, 2018), (Tran et al., 2023). (Frenzel, 2012; Gao et al., 1997; Gao et al., 2022; Gibson, 2014; Goldsmith, 2005; Golmie et al., 2003) 3. Measurement and Simulation Infrastructure The measurement and simulation infrastructure required for systematic impedance mismatch characterization encompasses the vector network analyzer for impedance measurement, time- domain reflectometry equipment for discontinuity location, noise figure analyzers for receive chain characterization, and electronic design automation tools for matching network synthesis and performance simulation. This section reviews the capabilities and calibration requirements of each instrument class, and describes the simulation methodologies that complement the physical measurements to provide a complete picture of the impedance mismatch impact across the operating frequency range (Pozar, 2012; Keysight Technologies, 2017). (Okonkwo et al., 2021; Okonkwo et al., 2020; Okonkwo et al., 2023; Okonkwo et al., 2024; Okonkwo et al., 2024; Okonkwo et al., 2024) 3.1 Vector Network Analyzer Calibration and S-Parameter Measurement The VNA is the primary instrument for RF mismatch characterization. Calibration removes the systematic errors introduced by the test port cables, connectors, and directional couplers, establishing an accurate measurement reference plane at the device under test. Full two-port SOLT (short-open-load-thru) calibration is the standard approach for most RF front-end measurements, providing corrections for directivity, source match, reflection tracking, transmission tracking, and load match errors (Marks, 1991), (Angelov et al., 1992). The calibration reference plane is established at the SMA connector attached to the PCB, or at on-board impedance calibration P-ISSN 2695- 1924 standards when in-situ characterization is required (Keysight, 2019), (Keysight, 2021). (Hayden, 2006; Lahtinen et al., 2023; Martens, 1997; Mohamed et al., 2022; Rytting, 1996; Spirent, 2020; Texas, 2023; Wen et al., 2022) (Obogo et al., 2021; Rahmat-Samii et al., 2015; Sanni et al., 2020) (Zhu et al., 2003; Zhu et al., 2005; Zorzi et al., 2010) Following calibration, VNA reflection coefficient measurements are taken at the antenna feed point, the RF switch input and output ports, and the LNA input with the receive path connected. The Smith chart display of these measurements allows the engineer to visualize the impedance trajectory across the operating frequency band and to immediately identify the interfaces where the impedance is furthest from the 50-ohm reference. The measured reflection data is exported for the cascade sensitivity calculation in Stage 3. The measurement is repeated after any mechanical change to the PCB, enclosure, or antenna clearance area, because these physical changes alter the antenna impedance and invalidate earlier measurements (Keysight Technologies, 2017). (Gomez et al., 2019; Gustrau, 2012; Hansen, 1998; Harrington, 2001; Hasan et al., 2011; Hassan et al., 2022) 3.2 Time-Domain Reflectometry for Discontinuity Location Time-domain reflectometry complements VNA measurements by providing spatial resolution of impedance discontinuities along PCB traces. The VNA can be configured as a TDR by applying an inverse Fourier transform to the measured S11 frequency-domain data, transforming the reflection spectrum into a time-domain reflectogram that shows the position of each discontinuity along the transmission path (Ogawa et al., 1996). A reflection appearing at a round-trip delay of 0.15 ns corresponds to a discontinuity approximately 10 mm from the reference plane in a medium with a dielectric constant of 4.0, typical of FR4 substrate. This localization capability enables engineers to identify whether a mismatch arises at a connector solder joint, a via transition, or the antenna feed pad rather than requiring invasive probing (Tran et al., 2023). (Okonkwo et al., 2024; Okoruwa et al., 2020; Olagunju et al., 2022; Olagunju et al., 2023; Olagunju et al., 2024; Oppenheim et al., 2010) 3.3 Noise Figure Measurement: Y-Factor Method The Y-factor method for noise figure measurement uses a calibrated noise source with a known excess noise ratio to excite the device under test through two noise temperature states (Dambrine et al., 1988). With the noise source in its hot state (T_hot = 290*(10^(ENR/10)) Kelvin) and cold state (T_cold approximately 290 K), the noise figure is determined from the ratio Y = N_hot/N_cold and the ENR value as F = (10^(ENR/10) - Y) / (Y - 1). For measurement of the mismatch-induced noise figure penalty, the standard setup is modified by inserting a calibrated mismatch network between the noise source and the LNA input, presenting a known reflection coefficient of controlled magnitude and phase. The resulting noise figure measurement, compared to the result with a matched source, directly quantifies the noise figure increase as a function of source mismatch (Hashim et al., 2022). 3.4 Load-Pull Characterization for PA Mismatch Analysis Load-pull measurement systems use a tunable impedance presented to the PA output by a mechanical or electronic impedance tuner to map the PA output power and efficiency as functions of the load impedance. The load impedance that maximizes power-added efficiency is identified P-ISSN 2695- 1924 from the load-pull contour map and used as the target impedance for the transmit matching network design. For IoT applications where battery life is critical, the efficiency-maximizing load impedance is typically preferred over the power-maximizing load impedance, because the marginal output power from the power-optimal match rarely justifies the battery life cost of operating the PA away from its most efficient point. The framework Stage 5 transmit matching network synthesis uses the load-pull data as its primary design input, providing a physically grounded basis for the matching component values rather than relying on simplified impedance estimates. (Haykin, 2002; Hernandez et al., 2023; Hiertz et al., 2010; Himmelfarb et al., 2021; Hirasawa et al., 1992; Howlader et al., 2009) 3.5 ADS Co-Simulation Workflow Advanced Design System provides an integrated environment for combining measured S- parameter data with circuit-level component models to predict the aggregate RF behavior of a front-end assembly. In the proposed framework, Touchstone. s2p files exported from the VNA are imported into ADS as two-port models for each characterized interface, replacing idealized 50- ohm terminations. The resulting circuit schematic accurately represents the actual measured impedance environment at each stage, and ADS harmonic balance simulations provide predictions of intermodulation products and EVM under drive conditions that account for the nonlinear device models and the actual mismatch loading (Escotte et al., 1993). (Oteri et al., 2022; Oyeleye et al., 2022; Ozowara et al., 2022; Pailloncy et al., 2009; Papoulis et al., 2002; Park et al., 2019) 4. The Proposed Modeling Framework The proposed seven-stage systematic framework synthesizes the measurement, analysis, and optimization methodologies reviewed in the preceding sections into a structured workflow that guides the RF engineer from the initial impedance budget specification through the prototype characterization to the production sensitivity verification. Each stage of the framework has defined inputs, analysis procedures, and outputs that link the preceding stage to the following stage, creating a traceable analysis chain from the top-level wireless link budget to the production test specification (Pozar, 2012; Gonzalez, 1997; Bowick et al., 2011). 4.1 Overall Architecture The proposed framework consists of four sequential stages, each building on the outputs of the preceding stage. Stage 1 characterizes the impedance mismatch profile at each RF interface using VNA measurements and Smith chart analysis. Stage 2 computes the per-stage performance penalties attributable to each interface's mismatch, covering noise figure degradation for receive- path interfaces and gain compression margin reduction and mismatch loss for transmit-path interfaces. Stage 3 assembles these per-stage penalties into a cascaded chain model using modified Friis expressions that incorporate the mismatch-corrected gain and noise figure values of each stage. Stage 4 integrates the cascade analysis into the link budget to compute effective sensitivity and link margin, performs a sensitivity ranking of the interface contributions, and computes maximum tolerable reflection coefficient specifications for each interface. (Oluwole et al., 2020) (Hualiang et al., 2004; Huang et al., 2008; Ibrahim et al., 2023; IEEE, 2005; IEEE, 2012; IEEE, 2016) (Oshoba et al., 2019) P-ISSN 2695- 1924 The framework is implemented as a modular computational workflow in which each stage can be re-executed independently as prototype hardware is revised. When a new antenna is mounted on a revised PCB, for example, only Stage 1 for the antenna interface and the downstream stages need to be re-run; the characterization results for unmodified interfaces carry forward. This iterative structure supports the rapid bring-up cycles typical of hardware development, where multiple board revisions may be produced within a single project week (Razavi, 2012), (Lee, 2004). (Park et al., 2023; Patel et al., 2021; Patrick et al., 2021; Patrick et al., 2020; Pedro et al., 2003; Perahia et al., 2013) (Hammed et al., 2023) 4.2 Stage 1: Interface Mismatch Characterization For each interface in the signal chain, the reflection coefficient magnitude and phase are extracted from VNA measurements across the operating frequency band, along with the worst-case return loss across the operating channel bandwidth. For two-port components such as the RF switch and balun, the transmission coefficient and its associated insertion loss are also extracted. These measurements are recorded in a structured format that feeds directly into the Stage 3 cascade computation, which combines the individual interface measurements into an aggregate sensitivity prediction. The measurement bandwidth should extend at least 20 percent beyond the operating channel on each side to capture any impedance anomalies at the band edges that could affect performance in the channel allocation extremes (Keysight Technologies, 2017). The frequency dependence of ML(f) is characterized at a frequency resolution sufficient to resolve the mismatch resonances within the operating channel. For a 40 MHz Wi-Fi channel, a 1 MHz frequency step provides 40 measurement points across the channel, capturing gain slope effects that would be invisible in a single-frequency evaluation. For Bluetooth channels occupying 2 MHz of bandwidth, a 100 kHz resolution is used. The band-averaged mismatch loss is computed as the arithmetic mean of ML(f) across the channel, and the peak mismatch loss is recorded separately for use in worst-case sensitivity analysis (Eldek et al., 2005). (IEEE, 2021; Ikpehai et al., 2019; Ilvonen et al., 2014; Imani et al., 2023; Ismail et al., 1994; Jarvis et al., 2022) 4.3 Stage 2: Per-Stage Performance Penalty Computation For each receive-path interface, the noise figure contribution is computed using the cascade noise figure relationship, accounting for the source impedance at that interface and the published noise parameters of the active devices that follow it in the signal chain. The computation uses the LNA minimum noise figure and optimal source reflection coefficient from the device datasheet, together with the measured source impedance at the LNA input port, to estimate the degradation of the LNA noise figure above its minimum achievable value. This degradation is then propagated through the Friis cascade formula to yield the contribution of each interface to the overall receive- path noise figure. The framework documentation for Stage 3 should record the source impedance at each interface, the assumed noise parameters, and the computed noise figure contribution for each stage, creating a traceable audit trail from the measured impedance data to the final sensitivity prediction (Gonzalez, 1997). (Perera et al., 2014; Peterson et al., 1998; Pozar, 1983; Pozar et al., 1987; Pozar et al., 1995; Proakis et al., 2006) For transmit-path interfaces, two penalty terms are computed. The first is the impedance mismatch loss, which reduces the effective transmit power delivered to the antenna feed port relative to the power available from the PA output. The second is the gain compression penalty, which quantifies P-ISSN 2695- 1924 the reduction in the PA output power at the one-decibel gain compression point caused by the reactive load mismatch. A PA driving a mismatched antenna load can enter compression at a lower drive level than when driving a matched load, reducing the usable output power range and potentially increasing the adjacent channel power ratio. The framework Stage 3 transmit analysis computes both penalties and combines them to determine the effective transmit EIRP reduction caused by the mismatch at the PA output interface. 4.4 Stage 3: Cascaded Chain Analysis The cascade analysis assembles the per-stage values into the modified Friis noise figure expression: (Shellhammer et al., 2001) (Jiang et al., 2021; Johansson et al., 2007; Jrad et al., 2023; Kay, 1993; Kenington, 2000; Khalid et al., 2021) where NF_eff_ant includes the antenna mismatch loss contribution, NF_eff_sw includes both the switch insertion loss and the switch-induced source impedance shift at the LNA input, and NF_LNA_mismatch is the LNA noise figure under the actual mismatched source. The gain terms G_ant and G_sw represent the available gains at each stage, set to 1-ML for passive elements. The cascaded NF_sys is then used to compute the receiver sensitivity as Sensitivity = -174 + 10log10(BW) + NF_sys + SNRmin (Razavi, 2012), (Agilent, 2010). (Huang et al., 2022) (Proakis et al., 2008; Qu et al., 2019; Qualcomm, 2021; Qureshi et al., 2022; Raab et al., 2002; Rappaport, 2002) 4.5 Stage 4: Link Budget Integration and Sensitivity Analysis The link budget is assembled from the cascade analysis outputs and the propagation model. The link margin LM is: (Rohde et al., 2019) 4.6 VNA Characterization Results The VNA characterization results from Stage 2 of the framework provide the empirical impedance data that grounds all subsequent cascade analysis and matching network synthesis steps. The characterization procedure measures the complex reflection coefficient at each RF port of the receive chain across the full operating frequency range, generates the corresponding Smith chart display for visual impedance assessment, and records the return loss at the nominal operating frequency for comparison against the Stage 1 impedance budget allocation. These results are archived with the calibration certificate identifier and the measurement date to support the traceability requirements of the production test documentation (Agilent Technologies, 2010; Keysight Technologies, 2012). (Kildal, 2000; Kim et al., 2002; Kim et al., 2005; Kim et al., 2024; Kong, 2000; Kraus et al., 2002) 5. Application to Wireless IoT Prototype Development The application of the seven-stage framework to real wireless IoT module development programs demonstrates its practical engineering value and validates the cascade sensitivity prediction against directly measured prototype sensitivity. The following subsections present two representative case studies: a Bluetooth 5.0 fitness tracker module and a dual-band Wi-Fi 6 IoT gateway module, both characterized using the framework methodology and compared against the sensitivity specification to assess the framework's predictive accuracy (Pozar, 2012; Bowick et al., 2011). (Raza et al., P-ISSN 2695- 1924 2017; Raza et al., 2021; Razavi, 2001; Reinhold, 2001; Rohde et al., 2000; Sadiku, 2014) (Aifuwa et al., 2020) 5.1 Bluetooth 5.0 Front-End Characterization Workflow The application of the proposed seven-stage framework to a Bluetooth 5.0 IoT module development program illustrates the practical engineering value of the systematic mismatch characterization approach. The module under consideration is a compact fitness tracker design incorporating a silicon chip antenna with a printed circuit board of dimensions 25 mm by 12 mm, a form factor that severely constrains the antenna ground plane geometry relative to the manufacturer's recommended clearance area. The Stage 1 impedance budget allocation establishes that the total mismatch loss budget across the receive chain must not exceed 1.2 dB to achieve the target sensitivity of minus 93 dBm at the 30.8 percent packet error rate threshold specified for Bluetooth LE conformance. This budget allocates 0.6 dB to the antenna interface, 0.35 dB to the RF switch, and 0.25 dB to the LNA input matching, providing clear quantitative targets for each matching network design stage. (Al-Sarawi et al., 2017; Boulis et al., 2003; Chang, 2022; Chen et al., 2021; Chiani et al., 2018; Gubbi et al., 2013; Kumuyi et al., 2024; Li et al., 2015) (Al-Fuqaha et al., 2015; Al-Sarawi et al., 2017; Mbonu et al., 2020; Sanchez-Iborra et al., 2016) The Stage 2 VNA characterization of the as-built prototype reveals that the antenna interface exhibits a return loss of only 6 dB at 2.44 GHz when mounted in the final PCB configuration with the wristband attachment points installed, corresponding to a mismatch loss of 1.05 dB at the worst-case channel frequency. This result exceeds the Stage 1 budget allocation for the antenna interface by 0.45 dB and predicts a total receive-path sensitivity of minus 91.3 dBm, which fails the minus 93 dBm specification by 1.7 dB. The Smith chart display of the antenna impedance locus shows that the impedance at 2.44 GHz is located in the inductive half of the chart at a distance from the 50-ohm center that corresponds to the measured return loss, identifying the reactive component of the impedance mismatch as the dominant contribution to the sensitivity shortfall. The framework immediately directs the engineer toward a capacitive matching element that will rotate the impedance locus toward the 50-ohm center on the Smith chart. (Kumar et al., 2022; Kumuyi et al., 2023; Ladapo et al., 2019; Ladapo et al., 2022; Ladapo et al., 2023; Ladapo et al., 2024a) The Stage 3 cascade sensitivity analysis using the VNA-measured interface impedances and the LNA datasheet noise parameters generates a complete sensitivity prediction for the as-built prototype, quantifying the contribution of each receive-path interface to the overall sensitivity deficit. The antenna interface contributes 1.05 dB of sensitivity loss, the RF switch contributes 0.62 dB of insertion loss, the LNA input mismatch contributes 0.18 dB, and the LNA noise figure contributes the fundamental 3.4 dB noise floor of the device. The cascade sum of these contributions predicts a sensitivity of minus 91.3 dBm, consistent with the direct measurement of minus 91.5 dBm performed in parallel with the VNA characterization, validating the cascade analysis to within 0.2 dB measurement uncertainty. This close agreement between the predicted and measured sensitivity confirms that the VNA-based cascade framework accurately captures the dominant loss mechanisms in the receive path. (Saleh et al., 1987; Sanni et al., 2022; Sanni et al., 2023; Sanni et al., 2023; Sanni et al., 2023; Sanni et al., 2022) P-ISSN 2695- 1924 The Stage 5 matching network synthesis for the antenna interface uses the measured impedance locus as the starting point and targets the 50-ohm reference impedance at the operating frequency of 2.44 GHz. The synthesis identifies a two-element L-network consisting of a 1.8 nanohenry series inductor and a 3.3 picofarad shunt capacitor as the smallest-component-count network that achieves the target impedance transformation, providing a predicted return loss of 18.5 dB at 2.44 GHz with a bandwidth of minus 10 dB return loss extending from 2.38 GHz to 2.50 GHz, covering the full Bluetooth frequency range. The component values correspond to standard E24 series values available from multiple surface-mount component manufacturers in 0201 package sizes compatible with the board layout constraints of the compact module design. The Stage 6 tolerance analysis using the nominal 5 percent component tolerances predicts a sensitivity distribution with a mean of minus 92.8 dBm and a standard deviation of 0.4 dB, indicating that approximately 84 percent of production units will meet the minus 92.0 dBm production test limit while maintaining 2 dB of guard band below the minus 93 dBm specification. 5.2 Wi-Fi 6 Dual-Band Module Mismatch Characterization The extension of the framework to a dual-band Wi-Fi 6 module that must simultaneously support 2.4 GHz and 5 GHz operation from a shared antenna element illustrates the multi-band matching challenge and the framework's approach to navigating the simultaneous constraints of both frequency bands. The module design uses a printed monopole antenna with a ground plane notch that creates a dual-band resonance at 2.45 GHz and 5.25 GHz, achieving a return loss greater than 8 dB across both operating bands in the unmatched condition when measured on the development board with the standard reference ground plane. When the antenna is integrated into the target product enclosure with the space constraints imposed by the mechanical design, the ground plane area available for the antenna is reduced, shifting the lower-band resonance to 2.31 GHz and degrading the return loss at 2.44 GHz to 5.2 dB. The framework Stage 2 characterization identifies this enclosure-induced impedance shift and establishes the required matching network transformation at both frequency bands as the starting point for the dual-band synthesis. (Ladapo et al., 2024b; Lansford et al., 2001; Lerstaveesin et al., 2008; Lewandowski et al., 2011; Li et al., 2006; Li et al., 2011) The dual-band matching network synthesis of Stage 5 for the Wi-Fi 6 module requires a three- element topology that provides independent control of the impedance transformation at 2.44 GHz and 5.25 GHz, because a two-element network provides insufficient degrees of freedom to simultaneously optimize the match at two widely separated frequencies. The framework identifies a pi-network topology consisting of a shunt capacitor at the antenna feed port, a series inductor, and a second shunt capacitor at the LNA input as the preferred architecture, because this topology allows the two shunt capacitor values to be tuned independently to control the match at the two frequency bands while the series inductor provides the coupling element between them. The component values are synthesized analytically using the dual-band impedance transformation equations from the filter design literature and refined through circuit simulation to account for the parasitic elements of the PCB layout. The final network achieves return losses of 15.3 dB at 2.44 GHz and 14.1 dB at 5.25 GHz, with mismatch losses of 0.12 dB and 0.14 dB respectively, well within the Stage 1 budget allocation of 0.6 dB at each band. (Sanni et al., 2021; Sanni et al., 2024; Sanni et al., 2024; Sanni et al., 2023; Sanni et al., 2021; Seki et al., 2005) (Oshoba et al., 2021) P-ISSN 2695- 1924 6. Discussion and Implications for IoT Hardware Development The empirical validation of the framework through its application to the Bluetooth 5.0 and Wi-Fi 6 prototype development programs demonstrates that the seven-stage approach reliably identifies impedance mismatch issues that would not be detected through functional bring-up testing alone. In both case studies, the Stage 2 VNA characterization revealed impedance conditions that would have produced a specification-failing sensitivity in the production product, and the Stage 5 matching network optimization restored the sensitivity to specification compliance before any additional prototype hardware was built. The cost avoidance from these pre-detection activities substantially exceeds the engineering time invested in the framework execution: each prevented prototype revision eliminates four to six weeks of schedule delay and the associated material, engineering, and test laboratory costs that accompany a hardware re-spin. (Oshoba et al., 2023b) (Oshoba et al., 2023) The broader implication of the framework for the IoT hardware development community is that systematic impedance characterization should be treated as a standard step in the wireless module development flow, comparable in importance to the power consumption characterization and the basic functional verification that are universally performed during prototype bring-up. The current practice in many development programs of deferring RF performance characterization until the regulatory pre-compliance testing phase, at which point the hardware design is frozen and only software-level compensation is available, results in shipped products with sensitivity performance that may be one to three decibels below the achievable optimum. Adopting the seven-stage framework at the prototype stage, rather than the pre-compliance stage, provides the engineering team with the measurement data and the matching network optimization tools needed to close the sensitivity gap before the hardware design is frozen. (Li et al., 2023; Liao et al., 2019; Lilian et al., 2020; Lim et al., 2009; Lim et al., 2021; Lin et al., 2017) The framework's approach to quantifying the economic value of impedance matching optimization provides development management with a principled basis for allocating engineering resources to RF performance work that may not be immediately visible in functional test results. The sensitivity shortfall attributable to impedance mismatch does not prevent the device from connecting to a Bluetooth or Wi-Fi network in the laboratory environment where the signal level is strong; it only manifests as reduced range, higher packet error rate, and higher power consumption in the real- world deployment environment where the link margin is tight. The framework's cascade sensitivity prediction makes this non-obvious performance impact visible at the prototype stage, enabling the development team to make informed decisions about whether the sensitivity improvement available from matching network optimization is worth the engineering investment before the product reaches the market. The answer, in most IoT applications where battery life and indoor range are competitive differentiators, is affirmative. (Semtech, 2020; Seun et al., 2023; Seun et al., 2024a; Seun et al., 2024b; Seye et al., 2021; Shirakawa et al., 1997) (Ahmed et al., 2019) (Hammed et al., 2021) (Hammed et al., 2023b) (Olatunde-Thorpe et al., 2020) (Aifuwa et al., 2023) (Nnabueze et al., 2021) (Olatunde-Thorpe et al., 2022) (Oshoba et al., 2020) (Olatunde-Thorpe et al., 2021) (Ogbuefi et al., 2021) (Ike et al., 2021) 7. Conclusions 7.1 Summary of Key Contributions P-ISSN 2695- 1924 This paper has presented a seven-stage systematic framework for the characterization and optimization of impedance mismatch in wireless IoT module receive and transmit paths. The framework addresses the gap between the component-level impedance specifications available from semiconductor manufacturers and the system-level sensitivity specifications required for wireless protocol conformance, providing a structured measurement and analysis workflow that quantifies the sensitivity impact of each interface in the RF signal chain and identifies the most effective targets for matching network optimization. The framework has been validated through its application to Bluetooth 5.0 and Wi-Fi 6 dual-band prototype development programs, demonstrating close agreement between the framework's cascade sensitivity predictions and the directly measured prototype sensitivity in both cases. The key contributions of this framework are the Stage 1 impedance budget allocation methodology, which translates the system-level sensitivity specification into quantitative mismatch loss allowances for each interface; the Stage 3 cascade sensitivity calculation, which combines the VNA-measured interface impedances with the LNA noise parameters to predict the system-level sensitivity without requiring direct sensitivity measurement; and the Stage 6 tolerance analysis, which extends the sensitivity prediction to the production distribution and provides the statistical basis for setting production test limits. These three contributions together enable the engineering team to connect the component-level RF design decisions directly to the system-level performance outcomes, creating a traceable analysis chain from the impedance specification to the production yield. Future extensions of the framework should address the multi-standard characterization requirements of cellular IoT devices, the temperature-dependent impedance behavior of antennas in thermal cycling environments, and the extension of the cascade model to account for the inter- protocol interference mechanisms that affect sensitivity in multi-protocol combo modules. The integration of machine learning techniques for automated matching network component value selection, guided by the historical characterization database accumulated across multiple product generations, represents a productive direction for reducing the engineering time required for the iterative optimization steps of Stages 4 through 6. The framework's fundamental contribution of making the impedance mismatch impact visible and quantifiable at the prototype stage will remain relevant regardless of the specific matching network technology or simulation tool used to implement the optimization steps. 7.2 Practical Implications and Recommendations The selection of the minimum number of frequency points at which the VNA impedance measurement must be performed to accurately characterize the antenna impedance across the Bluetooth or Wi-Fi operating band involves a tradeoff between measurement time, data storage, and the accuracy of the impedance interpolation between measurement points. For a single-band Bluetooth antenna with a 3 dB bandwidth of approximately 100 MHz centered at 2.44 GHz, a measurement grid of 401 frequency points with a 250-kHz step across the 2.3 to 2.55 GHz characterization range provides approximately 1 kHz per data point accuracy in the impedance trajectory, which is more than sufficient for the matching network synthesis accuracy required by Stage 5 of the framework. For a dual-band Wi-Fi antenna that must be characterized at both 2.4 GHz and 5 GHz, the measurement grid must cover both bands, typically requiring 1601 points across the 2.3 to 2.6 GHz and 4.9 to 5.9 GHz bands with a merged sweep, with care taken to ensure P-ISSN 2695- 1924 adequate measurement density around the resonant frequencies of each band where the impedance changes most rapidly with frequency. The effect of the balun, if present in the receive chain between the antenna and the single-ended LNA input, must be carefully accounted for in the Stage 2 impedance characterization and Stage 3 cascade analysis because the balun transforms both the impedance and the noise characteristics of the receive path. A balun with a nominal impedance ratio of 4:1, used to interface a 200-ohm balanced antenna to a 50-ohm unbalanced LNA input, introduces its own insertion loss and contributes a noise figure addition proportional to the insertion loss divided by the port mismatch factor at the LNA input. The framework Stage 2 measurement should characterize the antenna feed point impedance in balanced mode, using a balanced-to-unbalanced calibration technique or a balun de-embedding procedure, to obtain the true balanced impedance seen by the antenna element. Failure to account for the balun in the impedance characterization leads to an inaccurate cascade sensitivity prediction that systematically underestimates the sensitivity because the balun loss and mismatch contribution to the cascade noise figure are not included in the Stage 3 analysis. The role of the PCB manufacturing tolerance stack-up in the production distribution of antenna impedance is a practical consideration that determines how much margin the Stage 1 budget must include for manufacturing variation. PCB manufacturing tolerances that affect antenna impedance include the copper trace width tolerance, which affects the characteristic impedance of the antenna element feed line; the laminate dielectric constant tolerance, which affects the electrical length of the antenna element; and the copper thickness tolerance, which affects the radiation efficiency of electrically thin antenna elements. For a typical FR4 PCB with a 10-percent dielectric constant tolerance and a 5-percent copper thickness tolerance, the resulting antenna resonant frequency variation across production boards is approximately 25 to 40 MHz for a standard half-wave dipole antenna at 2.4 GHz, corresponding to a return loss variation at the nominal resonant frequency of 2 to 4 dB across the production distribution. The Stage 6 tolerance analysis must include this PCB fabrication variation as an uncertainty source in addition to the matching component tolerance, to provide a complete picture of the production sensitivity distribution. The antenna orientation sensitivity of the impedance characterization is a measurement quality consideration that is frequently overlooked in informal characterization procedures. Many antenna designs exhibit impedance that varies with the orientation of the device under test relative to the test environment, particularly when the PCB ground plane serves as part of the antenna radiating structure and the ground plane-to-laboratory-floor capacitance changes with the device height and orientation. The framework recommends that Stage 2 VNA measurements be performed with the device under test in the standard operating orientation at a standard height above the measurement table, with the measurement cable dressed in a consistent direction and with any hands-free support fixture reproduced consistently across characterization sessions. If the product is designed to operate in multiple orientations, such as a handheld device that may be used in portrait or landscape orientation, the VNA measurements should be repeated in each significant orientation and the worst-case impedance across orientations used as the basis for the Stage 3 cascade analysis. The verification of the RF switch isolation specification is a Stage 2 measurement that is often underperformed in practice because the switch insertion loss measurement is straightforward but the isolation measurement requires a more complex test setup involving signal injection into the inactive throw port while monitoring for signal coupling at the active throw port.