IIARD International Institute of Academic Research and Development

INTERNATIONAL JOURNAL OF COMPUTER SCIENCE AND MATHEMATICAL THEORY (IJCSMT )

E-ISSN 2545-5699
P-ISSN 2695-1924
VOL. 10 NO. 6 2024
DOI: 10.56201/ijcsmt.v10.no6.2024.pg15.31

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Classification Based Review of The Variants of Fast Fourier Transform (FFT) Algorithms

I.R. Tebepah, C.I. Amannah,

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Abstract

The Fast Fourier Transform (FFT) algorithm is based on efficiently computing the Discrete Fourier Transform (DFT) in different signal processing systems. It is an umbrella of different algorithms, with each having the capacity to perform relatively better than others depending on the scenario. This research was able to review and compare ten (10) FFT algorithms identifying strengths, weakness, and application using the stochastic method of comparison. The research summarised the findings in tabular form, thereby making it easy for researchers’’ select which FFT algorithm is most appropriate.

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References:

Akkad, G., Mansour, A., Hassan, B., Le Roy, F., & Najem, M. (2018,
November).
FFT radix-2 and radix-4 FPGA acceleration techniques using HLS
and HDL for digital communication. In 2018 IEEE International Multidisciplinary
Conference on Engineering Technology (IMCET) 1-5
Aravind Kumar, M., & Manjunatha Chari, K. (2017). An efficient pipelined architecture for
real-valued fast Fourier transform. International Journal of Electronics, 104(4),
692-708.
Ayinala, M., Brown, M., & Parhi, K. K. (2011). Pipelined parallel FFT architectures
via
folding transformation. IEEE Transactions on Very Large-Scale Integration (VLSI)
Systems, 20 (6), 1068-1081.
Ganguly, A., Chakraborty, A., & Banerjee, A. (2019). A novel VLSI design of
radix-4 DFT in current mode. International Journal of Electronics, 106(12), 1845-
Hassan, S. L. M., Sulaiman, N., & Halim, I. S. A. (2018) Low power
pipelined FFT processor architecture on FPGA. In 2018 9th IEEE
Control and System Graduate Research Colloquium (ICSGRC) , 31-
34
Kumar, A., Kumar, A., Devrari, A., & Singh, S. (2017). Design and FPGA Implementation
of 32-Point FFT Processor. In Proceeding of International Conference on Intelligent
Communication, Control and Devices, Advances in Intelligent Systems and
Computing, 285-292.
Mookherjee, S., DeBrunner, L., & DeBrunner, V. (2014, November). A high
throughput and low power radix-4 FFT architecture. In 2014 48th
Asilomar Conference on Signals, Systems and Computers, 1266-1270
Nash, J. G. (2018). Distributed-Memory-Based FFT Architecture and FPGA
Implementations. Electronics, 7(7), 116
Nguyen, N. H., Khan, S. A., Kim, C. H., & Kim, J. M. (2018). A high
performance, resource-efficient, reconfigurable parallel-pipelined
fft
processor
for
FPGA platforms.
Microprocessors
and
Microsystems, 60, 96-106.
Rauf, A., Pasha, M. A., & Masud, S. (2019). Towards design and
Automation of a scalable split-radix fft processor for high throughput
applications. Microprocessors and Microsystems, 65, 148-157.
Sood, S., Singh, A.., & Kumar, A. (2013). VHDL design of ofdm transreceiver
chip using variable FFT. Journal of Selected Areas in Microelectronics
(JSAM), Singaporean Journal of Scientific Research (SJSR), 5, 47-
Mittal, S., Khan, M., & Srinivas, S, (). On the suitability of bruun’s fft algorithm for software
defined radio
Engelberg, S., (2017). Elementary numbers theory and rader’s fft. Society For Industrial &
Applied Mathematics, 59 (1), 671-678
Garrido, M., (2017). A new representation of FFT algorithms using triangular matrices. IEEE
Transactions OnCircuit & System
Duan, B., Wang, W., Li, X., Zhang, C., Zhang, P., & Sun, N., (2011). Floating-point mixed
radix fft core generation for fpga and comparison with gpu and cpu. IEEE
Ganguly, A., Chakraborty, A., & Banorjee, A., (2019). A novel vlsi design of radix-4 dft in
Current mode. International Journal of Electronics
Tolimieri, R., Lu, C., & Johnson, R., (1990). Modified winograd fft algorithm and its variants
For transform size N= pk and their implementation. Advances in Applied
Mathematics, 10, 228-251
Silverman, H., (1977). An introduction to programming the winograd fourier transform
Algorithm (wfta). IEEE Transactions on Acoustics speech and Signal Processing, 25
(2), 152-165
Duhamel, P., & Vetterli, M., (1990). Fast fourier transform: a tutorial review & a state of the
art. Signal Processing, 19, 259-299
Su, T., Yang, M., Jin,T., & Flesch, R., (2018). Power harmonic and inerharmonic detection
Method in renewable power based on nuttall double-window all-phase fft algorithm.
IET Journals.
Sorenson, H.V., Heideman, M.T., & Burrus.C.S. (1986). On computing the
split-radix fft. IEEE Transactions on Acoustics, Speech, and Signal
Processing, ASSP-34(1):152–156
Pierre, D., (1986). Implementation of split-radix fft algorithms for complex, real,
and real- symmetric data. IEEE Transactions on Acoustics, Speech, and Signal
Processing, ASSP- 34 (2):285–295.
Clive, T., (1983) A note on prime factor fft algorithms. Journal of
Computational Physics,
58, 198–204
Clive, T., (1985). Implementation of a self-sorting in-place prime factor fft algorithm.
Journal of Computational Physics, 58, 283–299.
Teymourzadeh, R., Abigo, M. J., & Hoong, M. V. (2014). Static quantised
radix-2 fast Fourier transform (FFT)/inverse FFT processor
for constraints analysis. International Journal of Electronics,
101(2), 231-240.
Wey, C. L., Lin, S. Y., & Tang, W. C. (2007, May). Efficient memory-based
FFT processors for OFDM applications. In 2007 IEEE International
Conference on Electro/Information Technology (pp. 345-350). IEEE.
Wang, J., Xie, Y., & Yang, C. (2019). Single channel pipelined variable-length
FFT processor design. The Journal of Engineering, 2019(21), 7709-
Wang, B., Zhang, Q., Ao, T., & Huang, M. (2010, January). Design of
pipelined FFT processor based on FPGA. In 2010 Second
International Conference on computer modeling and simulation (Vol.
4, pp. 432-435). IEEE.
Wang, S. S., & Li, C. S. (2008). An area-efficient design of variable-length
fast Fourier transform processor. Journal of Signal Processing Systems, 51(3),
245-256.
Yang, C., Xie, Y. Z., Chen, L., Chen, H., & Deng, Y. (2015). Design of a
configurable fixed-point FFT processor, pp(1-4).
Yang, C., Wei, C., Xie, Y., Chen, H., & Ma, C. (2017). Area-efficient mixed-
radix variable-length FFT processor. IEICE Electronics Express, 14(10),
20170232-
20170232.

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